Many types of memory chip structures are used in the course of digital circuitry, the simplest memory structure of which is when the memory chips are merely one bit wide. For example, a memory with organization such as a 4K by 1 represents the situation where the memory structure is one bit wide and the memory unit can store 4,092 bits of memory and each individual bit-space can be addressed in order to output the particular data bit which resides in that memory space.
The conventional parity check detection circuitry which is used for such a memory structure (which is made up by one bit wide memory chips) is provided by adding a single parity bit to each word wherein the parity bit is stored into the memory together with the written-in word during the Write time. Subsequently, when the particular word and its parity bit is read out, then a new parity check is accomplished by checking the parity for the particular word that was read out during the Read time.
This scheme works adequately as long as the memory chips used are merely one bit wide in their organization since, in this case, any single chip failure would result in a single bit failure and thus be detected by the Read-out of the word and its parity bit.
However, increasingly today, the memory chips used in memory structure are organized according to multi-bit widths, such as 1K by 4. Under these conditions the normal detection scheme of adding a parity bit to the writing of a wide word and then detecting the parity bit after the reading out of the word would cause the system to miss many single chip failures since this can result in no failure to a 4 bit failure.
Since the memory structures used very often consist of multi-bit width memory chips, as for example, in such designs as control stores and look-up tables, it is most desirable to have a more accurate parity detection scheme to overcome the inaccuracies inherent in the prior types of parity checking.